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7.5 I/O Transfer Function
The I/O transfer to or from the Card can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the –
IOIS16 signal is asserted by the Card, otherwise it is de-asserted. When a 16 bit transfer is attempted, and the –
IOIS16 signal is not asserted, the system must generate a pair of 8 bit references to access the Word’s even and
odd Bytes. The Card permits both 8 and 16 bit accesses to all of its I/O addresses, so – IOIS16 is asserted for all
addresses (see Table 39).
Table 39: I/O Function
Function Code
Standby Mode
Byte Input Access
(8 bits)
Byte Output Access
(8 bits)
Word Input Access (16 bits)
Word Output Access (16 bits)
I/O Read Inhibit
I/O Write Inhibit
High Byte Input Only (8 bits)
High Byte Output Only (8 bits)
-REG
X
L
L
L
L
L
L
H
H
L
L
-CE2
H
H
H
H
H
L
L
X
X
L
L
-CE1
H
L
L
L
L
L
L
X
X
H
H
A0
X
L
H
L
H
L*
L*
X
X
X
X
-IORD
X
L
L
H
H
L
H
L
H
L
H
-IOWR
X
H
H
L
L
H
L
H
L
H
L
D15 to D8
High Z
High Z
High Z
Don’t Care
Don’t Care
Odd Byte
Odd Byte
Don’t Care
High Z
Odd Byte
Odd Byte
D7 to D0
High Z
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Even Byte
Don’t Care
High Z
High Z
Don’t Care
* Address A0 must be low for all word accesses.
7.6 Common Memory Transfer Function
The Common Memory transfer to or from the Card permits both 8 or 16 bit access to all of the Common Memory
addresses (see Table 40).
Table 40: Common Memory Function
Function Code
Standby Mode
Byte Read Access
(8 bits)
Byte Write Access
(8 bits)
Word Read Access (16 bits)
Word Write Access (16 bits)
Odd Byte Read Only (8 bits)
Odd Byte Write Only (8 bits)
-REG
X
H
H
H
H
H
H
H
H
-CE2
H
H
H
H
H
L
L
L
L
-CE1
H
L
L
L
L
L
L
H
H
A0
X
L
H
L
H
L*
L*
X
X
-OE
X
L
L
H
H
L
H
L
H
-WE
X
H
H
L
L
H
L
H
L
D15 to D8
High Z
High Z
High Z
Don’t Care
Don’t Care
Odd Byte
Odd Byte
Odd Byte
Odd Byte
D7 to D0
High Z
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Even Byte
High Z
Don’t Care
* Address A0 must be low for all word accesses.
7.7 True IDE Mode I/O Function
The Card can be configured in a True IDE Mode of operation. It is configured in this mode only when the – OE
signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PC card protocol
and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. No Memory
or Attribute Registers are accessible to the host. The Set Feature Command can be used to put the device in 8 bit
Mode (see Table 41).
Removing and reinserting the Card while the host computer’s power is on will reconfigure the Card to PC Card ATA
mode.
Table 41: True IDE Mode I/O Function
Function Code
Invalid Mode
Standby Mode
Task File Write
Task File Read
PIO Data Register Write
DMA Data Register Write
PIO Data Register Read
- CS1
L
L
L
X
X
H
H
H
H
H
H
- CS0
L
X
X
L
L
H
L
L
L
L
L
A2 to A0
X
X
X
X
X
X
1h-7h
1h-7h
0
X
0
-DMACK
X
L
L
L
L
H
H
H
H
L
H
- IORD
X
L
X
L
X
X
H
L
H
H
L
- IOWR
X
X
L
X
L
X
L
H
L
L
H
D15 to D8
Undefined
In/Out
Undefined Out
Undefined In
Undefined Out
Undefined In
High Z
Don’t Care
High Z
Odd-Byte In
Odd-Byte In
Odd-Byte Out
D7 to D0
Undefined In/Out
Undefined Out
Undefined In
Undefined Out
Undefined In
High Z
Data In
Data Out
Even-Byte In
Even-Byte In
Even-Byte Out
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 46 of 102
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